Infineon TRAVEO T2G - 28.4.1.1.10 TCPWM_GRP_CNT_LINE_SEL

Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.10 TCPWM_GRP_CNT_LINE_SEL
Description:
Counter line selection register
Address:
0x40380028
Offset:
0x28
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x32
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] COMPL_OUT_SEL [6:4] None [3:3] OUT_SEL [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:2 OUT_SEL RW RW 2 Selects the source for the output signal 'line_out'.
Default setting is the PWM signal 'line'. Other settings
are useful for Stepper Motor Control.
This field has a function in PWM and PWM_PR modes
only.
Note: The output signal of this selection can be further
modified by the stop / kill logic and line_out polarity
setting (CTRL.QUAD_ENCODING_MODE[0]).
L 0 fixed '0'
H 1 fixed '1'
PWM 2 PWM signal 'line'
PWM_INV 3 inverted PWM signal 'line'
Z 4 The output 'line_out' is not driven by the TCPWM.
Instead the port default level configuration applies, e.g.
'Z' (high impedance).
Note: This is realized by driving the output
'line_out_en' to 0.
Reserved5 5 N/A
Reserved6 6 N/A
Reserved7 7 N/A
4:6 COMPL_OUT_SEL RW RW 3 Selects the source for the output signal
'line_compl_out'. Default setting is the inverted PWM
signal 'line'. Other settings are useful for Stepper Motor
Control.
This field has a function in PWM and PWM_PR modes
only.
Note: The output signal of this selection can be further
modified by the stop / kill logic and line_compl_out
polarity setting (CTRL.QUAD_ENCODING_MODE[1]).
L 0 fixed '0'
H 1 fixed '1'
1805
2022-04-18
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