Infineon TRAVEO T2G - 5.1.51 CPUSS_PROTECTION

Technical Reference Manual 002-29852 Rev. *B
5.1.51 CPUSS_PROTECTION
Description:
Protection status
Address:
0x402020C4
Offset:
0x20C4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] STATE [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:2 STATE RW R 0 Protection state:
'0': UNKNOWN.
'1': VIRGIN.
'2': NORMAL.
'3': SECURE.
'4': DEAD.
The following state transitions are allowed (and
enforced by HW):
- UNKNOWN => VIRGIN/NORMAL/SECURE/DEAD
- NORMAL => DEAD
- SECURE => DEAD
An attempt to make a NOT allowed state transition will
NOT affect this register field.
754
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers