Infineon TRAVEO T2G - 23.9.41 SCB_INTR_S

Technical Reference Manual 002-29852 Rev. *B
23.9.41 SCB_INTR_S
Description:
Slave interrupt request
Address:
0x40600F40
Offset:
0xF40
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained In DeepSleep power mode: HW clears the interrupt causes
to '0', when coming out of DeepSleep power mode. In addition, HW clears the interrupt causes
to '0', when the IP is disabled. As a result, the interrupt causes are only available in
Active/Sleep power modes; they are generated by internally clocked logic (this logic operates
on a clock that is only available in Active/Sleep power modes).
The interrupt causes should only be used for internally clocked operation; i.e. EC_OP is '0'.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name I2C
_GENERAL
[7:7]
I2C_ADDR
_MATCH
[6:6]
I2C_START
[5:5]
I2C_STOP
[4:4]
I2C_WRITE
_STOP
[3:3]
I2C_ACK
[2:2]
I2C_NACK
[1:1]
I2C_ARB_L
OST [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] SPI_BUS_E
RROR
[11:11]
SPI_EZ_ST
OP [10:10]
SPI_EZ
_WRITE
_STOP
[9:9]
I2C_BUS_E
RROR [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 I2C_ARB_LOST RW1C RW1S 0 I2C slave lost arbitration: the value driven on the SDA
line is not the same as the value observed on the SDA
line (while the SCL line is '1'). This should not occur, it
represents erroneous I2C bus behavior. In case of lost
arbitration, the I2C slave state machine aborts the
ongoing transfer. The Firmware may decide to clear
the TX and RX FIFOs in case of this error.
1 I2C_NACK RW1C RW1S 0 I2C slave negative acknowledgement received. Set to
'1', when the slave receives a NACK (typically after the
slave transmitted TX data).
2 I2C_ACK RW1C RW1S 0 I2C slave acknowledgement received. Set to '1', when
the slave receives a ACK (typically after the slave
transmitted TX data).
1439
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers