Infineon TRAVEO T2G - 2.3.9.6.12 CANFD_CH_ECR

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.12 CANFD_CH_ECR
Description:
Error Counter Register
Address:
0x40520040
Offset:
0x40
Retention:
Retained
IsDeepSleep:
No
Comment:
Read side effect, except if read from debug host
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TEC [7:0]
Bits 15 14 13 12 11 10 9 8
Name RP [15:15] REC [14:8]
Bits 23 22 21 20 19 18 17 16
Name CEL [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 TEC R RW 0 Transmit Error Counter
Actual state of the Transmit Error Counter, values
between 0 and 255
8:14 REC R RW 0 Receive Error Counter
Actual state of the Receive Error Counter, values
between 0 and 127
15 RP R RW 0 Receive Error Passive
0= The Receive Error Counter is below the error
passive level of 128
1= The Receive Error Counter has reached the error
passive level of 128
16:23 CEL R RW1C 0 CAN Error Logging
The counter is incremented each time when a CAN
protocol error causes the Transmit Error Counter
or the Receive Error Counter to be incremented. It is
reset by read access to CEL. The counter stops
at 0xFF; the next increment of TEC or REC sets
interrupt flag IR.ELO.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers