Infineon TRAVEO T2G - 4.13.2.3 CM4_DWT_CPICNT

Technical Reference Manual 002-29852 Rev. *B
4.13.2.3 CM4_DWT_CPICNT
Description:
CPI Count register
Address:
0xE0001008
Offset:
0x8
Retention:
Retained
IsDeepSleep:
No
Comment:
The CPICNT register characteristics are:
Purpose: Counts additional cycles required to execute multi-cycle instructions and instruction
fetch stalls.
Usage constraints: The counter initializes to 0 when software enables its counter overflow
event by setting the CTRL.CPIEVTENA bit to 1.
Configurations:
Implemented only when CTRL.NOPRFCNT is RAZ, see Control register, CTRL on Arm TRM
page C1-797.
If CTRL.NOPRFCNT is RAO, indicating that the implementation does not include the profiling
counters, this register is UNK/SBZP.
Attributes: See Table C1-21 on page C1-797.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CPICNT [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 CPICNT RW RW 0 Base instruction overhead counter. Counts one on
each cycle when all of the following are true:
- No instruction is executed.
- No load-store operation is in progress, see LSU
Count register, DWT_LSUCNT on
page C1-803.
- No exception-entry or exception-exit operation is in
progress, see Exception Overhead Count register,
DWT_EXCCNT on Arm TRM page C1-802.
- Not in a power saving mode, see Sleep Count
register, DWT_SLEEPCNT on page C1-802.
The definition of 'no instruction is executed' is
IMPLEMENTATION DEFINED. ARM recommends that
this counts each cycle on which no instruction is
retired.
An event is emitted on counter overflow. Initialized to
zero when DWT_CTRL.CPIEVTENA transitions from 0
to 1.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers