Infineon TRAVEO T2G - 26.8.50.9 MCWDT_INTR_MASK

Technical Reference Manual 002-29852 Rev. *B
26.8.50.9 MCWDT_INTR_MASK
Description:
MCWDT Interrupt Mask Register
Address:
0x402680A8
Offset:
0xA8
Retention:
Retained
IsDeepSleep:
No
Comment:
This register controls whether a subcounter interrupt is forwarded to the corresponding
processor. All masks block the interrupt when 0 and forward the interrupt when 1.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CTR2_INT
[2:2]
CTR1_INT
[1:1]
CTR0_INT
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CTR0_INT RW R 0 Interrupt Mask for sub-counter 0 for warning interrupt.
The bit controls if the interrupt is forwarded to the
CPU. The interrupt is blocked when the value of the bit
is 0. The interrupt is forwarded if the value of the bit is
1.
1 CTR1_INT RW R 0 Interrupt Mask for sub-counter 1 for warning interrupt.
The bit controls if the interrupt is forwarded to the
CPU. The interrupt is blocked when the value of the bit
is 0. The interrupt is forwarded if the value of the bit is
1.
2 CTR2_INT RW R 0 Interrupt Mask for sub-counter 2. The bit controls if the
interrupt is forwarded to the CPU. The interrupt is
blocked when the value of the bit is 0. The interrupt is
forwarded if the value of the bit is 1.
1713
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers