Infineon TRAVEO T2G - 2.3.9.6.4 CANFD_CH_TEST

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.4 CANFD_CH_TEST
Description:
Test Register
Address:
0x40520010
Offset:
0x10
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RX [7:7] TX [6:5] LBCK [4:4] CAT [3:3] CAM [2:2] TAT [1:1] TAM [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TAM RW R 0 ASC is not supported by M_TTCAN
Test ASC Multiplexer Control
Controls output pin m_ttcan_ascm in test mode, ORed
with the signal from the FSE
0= Level at pin m_ttcan_ascm controlled by FSE
1= Level at pin m_ttcan_ascm = '1'
1 TAT RW R 0 ASC is not supported by M_TTCAN
Test ASC Transmit Control
Controls output pin m_ttcan_asct in test mode, ORed
with the signal from the FSE
0= Level at pin m_ttcan_asct controlled by FSE
1= Level at pin m_ttcan_asct = '1'
2 CAM RW R 0 ASC is not supported by M_TTCAN
Check ASC Multiplexer Control
Monitors level at output pin m_ttcan_ascm.
0= Output pin m_ttcan_ascm = '0'
1= Output pin m_ttcan_ascm = '1'
3 CAT RW R 0 ASC is not supported by M_TTCAN
Check ASC Transmit Control
Monitors level at output pin m_ttcan_asct.
0= Output pin m_ttcan_asct = '0'
4 LBCK RW R 0 Loop Back Mode
0= Reset value, Loop Back Mode is disabled
1= Loop Back Mode is enabled (see Section 3.1.9,
Test Modes)
5:6 TX RW R 0 Control of Transmit Pin
00 Reset value, m_ttcan_tx controlled by the CAN
Core, updated at the end of the CAN bit time
01 Sample Point can be monitored at pin m_ttcan_tx
10 Dominant ('0') level at pin m_ttcan_tx
11 Recessive ('1') at pin m_ttcan_tx
7 RX R R Undefined Receive Pin
Monitors the actual value of pin m_ttcan_rx
0= The CAN bus is dominant (m_ttcan_rx = '0')
1= The CAN bus is recessive (m_ttcan_rx = '1')
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers