Infineon TRAVEO T2G - 4.13.11.15 CM4_TPIU_CLAIMCLR

Technical Reference Manual 002-29852 Rev. *B
4.13.11.15 CM4_TPIU_CLAIMCLR
Description:
Claim Tag Clear Register
Address:
0xE008EFA4
Offset:
0xFA4
Retention:
Retained
IsDeepSleep:
No
Comment:
This register forms one half of the Claim Tag value. This location enables individual bits to be
cleared, write, and returns the current Claim Tag value, read. The width (n) of this register can
be determined from reading the Claim Tag Set Register.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] TAG [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 TAG RW1C R 0 A bit programmable register bank that is zero at reset.
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2022-04-18
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