Infineon TRAVEO T2G - 14.2.27.5 FLASHC_INTR_SET

Technical Reference Manual 002-29852 Rev. *B
14.2.27.5 FLASHC_INTR_SET
Description:
Interrupt Set
Address:
0x4024F024
Offset:
0x24
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] INTR_SET
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 INTR_SET RW1S A 0 Write INTR_SET field with '1' to set corresponding
INTR field (a write of '0' has no effect).
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers