Infineon TRAVEO T2G - 22.5.1.8.3 PROT_SMPU_SMPU_STRUCT_ADDR1

Technical Reference Manual 002-29852 Rev. *B
22.5.1.8.3 PROT_SMPU_SMPU_STRUCT_ADDR1
Description:
SMPU region address 1 (master structure)
Address:
0x40232020
Offset:
0x20
Retention:
Retained
IsDeepSleep:
No
Comment:
This register defines a SMPU address region. The address region is fixed, the region size is
64 B (two 32 B subregions within a 256 B region) and includes the ADDR0, ATT0, ADDR1 and
ATT0 registers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SUBREGION_DISABLE [7:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR24 [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR24 [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR24 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 SUBREGION_DISABLE R R SUBREGION
_DISABLE
_DEF1
This field is used to individually disabled the eight
equally sized subregions in which a region is
partitioned. Subregion disable:
Bit 0: subregion 0 disable.
Bit 1: subregion 1 disable.
Bit 2: subregion 2 disable.
Bit 3: subregion 3 disable.
Bit 4: subregion 4 disable.
Bit 5: subregion 5 disable.
Bit 6: subregion 6 disable.
Bit 7: subregion 7 disable.
Two out of a total of eight 32 B subregions are
enabled. These subregions includes region structures
0 and 1.
Note: this field is read-only.
8:31 ADDR24 R R ADDR
_DEF1
This field specifies the most significant bits of the 32-
bit address of an address region.
'ADDR_DEF1': base address of structure.
Note: this field is read-only.
1331
2022-04-18
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