Infineon TRAVEO T2G - 26.8.44 CLK_TRIM_ILO0_CTL

Technical Reference Manual 002-29852 Rev. *B
26.8.44 CLK_TRIM_ILO0_CTL
Description:
ILO0 Trim Register
Address:
0x40263014
Offset:
0x3014
Retention:
Retained
IsDeepSleep:
No
Comment:
Trims ILO frequency. Determined during manufacturing sort/class, but may be updated in the
field to calibrate voltage and temperature conditions. This register is protected by
WDT_CTL.WDT_LOCK. ILO0 configuration and trims are reset by XRES and power-related
resets, unless configured otherwise.
Default:
0x52C
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] ILO0_FTRIM [5:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] ILO0_MONTRIM [11:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:5 ILO0_FTRIM RW A 44 ILO0 frequency trims. LSB step size is 1.5 percent
(typical) of the frequency.
8:11 ILO0_MONTRIM RW A 5 ILO0 internal monitor trim.
1690
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers