Infineon TRAVEO T2G - 12.12.8 EVTGEN_REF_CLOCK_CTL

Technical Reference Manual 002-29852 Rev. *B
12.12.8 EVTGEN_REF_CLOCK_CTL
Description:
Reference clock control
Address:
0x403F0030
Offset:
0x30
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name INT_DIV [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 INT_DIV RW R 0 Divider control for clk_ref_div:
'0': Divide by 1.
...
'255': Divide by '256'.
Fclk_ref_div = Fclk_ref / (INT_DIV + 1)
903
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers