Infineon TRAVEO T2G - 3.8.3.21 CM0 P_SCS_MPU_CTRL

Technical Reference Manual 002-29852 Rev. *B
3.8.3.21 CM0P_SCS_MPU_CTRL
Description:
MPU Control Register
Address:
0xE000ED94
Offset:
0xD94
Retention:
Retained
IsDeepSleep:
No
Comment:
Enables the MPU, and when the MPU is enabled, controls whether the default memory map is
enabled as a background region for privileged accesses, and whether the MPU is enabled for
HardFaults and NMIs.
If no regions are enabled and the PRIVDEFENA and ENABLE bits are set, only privileged
code can execute from the system address map.
If the MPU is not implemented, this register is RAZ/WI.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] PRIVDEFEN
A [2:2]
HFNMIENA
[1:1]
ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 ENABLE RW R 0 Enables the MPU:
0: The MPU is disabled. Privileged and unprivileged
accesses use the
default memory map.
1: The MPU is enabled.
1 HFNMIENA RW R 0 The meaning of this bit is:
0: disables the MPU for HardFaults and NMIs.
1: when the ENABLE bit is set to 1, enables the MPU
for HardFaults and NMIs.
Note: If HFNMIENA is set to 1 when ENABLE is set to
0, behavior is UNPREDICTABLE.
2 PRIVDEFENA RW R 0 When the ENABLE bit is set to 1, the meaning of this
bit is:
0: Disables the default memory map. Any instruction or
data access that does not access a defined region
faults.
1: Enables the default memory map as a background
region for privileged access. The system address map
on Arm TRM page B3-258 describes the default
memory map.
When the ENABLE bit is set to 0, the processor
ignores the PRIVDEFENA bit.
182
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers