Infineon TRAVEO T2G - 23.9.45 SCB_INTR_TX

Technical Reference Manual 002-29852 Rev. *B
23.9.45 SCB_INTR_TX
Description:
Transmitter interrupt request
Address:
0x40600F80
Offset:
0xF80
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The register fields are not retained In DeepSleep power mode: HW clears the interrupt causes
to '0', when coming out of DeepSleep power mode. In addition, HW clears the interrupt causes
to '0', when the IP is disabled. As a result, the interrupt causes are only available in
Active/Sleep power modes; they are generated by internally clocked logic (this logic operates
on a clock that is only available in Active/Sleep power modes).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name BLOCKED
[7:7]
UNDERFLOW
[6:6]
OVERFLOW
[5:5]
EMPTY
[4:4]
None [3:2] NOT_FULL
[1:1]
TRIGGER
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] UART_ARB
_LOST
[10:10]
UART
_DONE
[9:9]
UART
_NACK
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TRIGGER RW1C RW1S 0 Less entries in the TX FIFO than the value specified by
TX_FIFO_CTRL.TRIGGER_LEVEL.
Only used in FIFO mode.
1 NOT_FULL RW1C RW1S 0 TX FIFO is not full. Dependent on
CTRL.MEM_WIDTH: (FF_DATA_NR =
EZ_DATA_NR/2)
MEM_WIDTH is '0': # entries != FF_DATA_NR.
MEM_WIDTH is '1': # entries != FF_DATA_NR/2.
MEM_WIDTH is '2': # entries != FF_DATA_NR/4.
Only used in FIFO mode.
4 EMPTY RW1C RW1S 0 TX FIFO is empty; i.e. it has 0 entries.
Only used in FIFO mode.
5 OVERFLOW RW1C RW1S 0 Attempt to write to a full TX FIFO.
Only used in FIFO mode.
6 UNDERFLOW RW1C RW1S 0 Attempt to read from an empty TX FIFO. This happens
when SCB is ready to transfer data and EMPTY is '1'.
Only used in FIFO mode.
7 BLOCKED RW1C RW1S 0 SW cannot get access to the EZ memory (EZ data
access), due to an externally clocked EZ access. This
may happen when STATUS.EC_BUSY is '1'.
8 UART_NACK RW1C RW1S 0 UART transmitter received a negative
acknowledgement in SmartCard mode. Set to '1', when
event is detected. Write with '1' to clear bit.
1445
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers