Technical Reference Manual 002-29852 Rev. *B
14.2.27.7 FLASHC_INTR_MASKED
Description:
Interrupt Masked
Address:
0x4024F02C
Offset:
0x2C
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] INTR
_MASKED
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 INTR_MASKED R W 0 Logical and of corresponding request and mask fields.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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