Technical Reference Manual 002-29852 Rev. *B
3.8.3.13 CM0P_SCS_AIRCR
Description:
Application Interrupt and Reset Control Register
Address:
0xE000ED0C
Offset:
0xD0C
Retention:
Retained
IsDeepSleep:
No
Comment:
Sets or returns interrupt control data.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] SYSRESETR
EQ [2:2]
VECTCLRAC
TIVE [1:1]
None [0:0]
Bits 15 14 13 12 11 10 9 8
Name ENDIANNES
S [15:15]
None [14:8]
Bits 23 22 21 20 19 18 17 16
Name VECTKEY [23:16]
Bits 31 30 29 28 27 26 25 24
Name VECTKEY [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
1 VECTCLRACTIVE RW1C R 0 Clears all active state information for fixed and
configurable
exceptions. The effect of writing a 1 to this bit if the
processor is not halted in Debug state is
UNPREDICTABLE.
2 SYSRESETREQ RW1S R 0 System Reset Request. Writing 1 to this bit asserts a
signal to request a reset by the external system. This
will cause a full system reset of the CPU and all other
components in the device. See Reset management on
Arm TRM page B1-240 for more information.
15 ENDIANNESS R 0 Indicates the memory system data endianness:
0 little endian
1 big endian.
See Endian support on page A3-44 for more
information.
16:31 VECTKEY RW R X Vector Key. The value 0x05FA must be written to this
register, otherwise the register write is not performed.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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