Infineon TRAVEO T2G - 14.2.20 FLASHC_CM4_CA_STATUS1

Technical Reference Manual 002-29852 Rev. *B
14.2.20 FLASHC_CM4_CA_STATUS1
Description:
CM4 cache status 1
Address:
0x402404C4
Offset:
0x4C4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TAG [7:0]
Bits 15 14 13 12 11 10 9 8
Name TAG [15:8]
Bits 23 22 21 20 19 18 17 16
Name TAG [23:16]
Bits 31 30 29 28 27 26 25 24
Name TAG [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 TAG R W Undefined See CM0_CA_STATUS1.
957
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers