Infineon TRAVEO T2G - 19.2.26 CH 25; 19.2.27 CH 26; 19.2.28 CH 27; 19.2.29 CH 28

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR1_CH24_RANGE_CTL
0x40901E0C FULL Range thresholds
PASS0_SAR1_CH24_INTR
0x40901E10 FULL Interrupt request register.
PASS0_SAR1_CH24_INTR_SET
0x40901E14 FULL Interrupt set request register
PASS0_SAR1_CH24_INTR_MASK
0x40901E18 FULL Interrupt mask register.
PASS0_SAR1_CH24_INTR_MASKED
0x40901E1C FULL Interrupt masked request register
PASS0_SAR1_CH24_WORK
0x40901E20 FULL Working data register
PASS0_SAR1_CH24_RESULT
0x40901E24 FULL Result data register
PASS0_SAR1_CH24_GRP_STAT
0x40901E28 FULL Group status register
PASS0_SAR1_CH24_ENABLE
0x40901E38 FULL Enable register
PASS0_SAR1_CH24_TR_CMD
0x40901E3C FULL Software triggers
19.2.26 CH 25
Register Name Address Permission Description
PASS0_SAR1_CH25_TR_CTL
0x40901E40 FULL Trigger control.
PASS0_SAR1_CH25_SAMPLE_CTL
0x40901E44 FULL Sample control.
PASS0_SAR1_CH25_POST_CTL
0x40901E48 FULL Post processing control
PASS0_SAR1_CH25_RANGE_CTL
0x40901E4C FULL Range thresholds
PASS0_SAR1_CH25_INTR
0x40901E50 FULL Interrupt request register.
PASS0_SAR1_CH25_INTR_SET
0x40901E54 FULL Interrupt set request register
PASS0_SAR1_CH25_INTR_MASK
0x40901E58 FULL Interrupt mask register.
PASS0_SAR1_CH25_INTR_MASKED
0x40901E5C FULL Interrupt masked request register
PASS0_SAR1_CH25_WORK
0x40901E60 FULL Working data register
PASS0_SAR1_CH25_RESULT
0x40901E64 FULL Result data register
PASS0_SAR1_CH25_GRP_STAT
0x40901E68 FULL Group status register
PASS0_SAR1_CH25_ENABLE
0x40901E78 FULL Enable register
PASS0_SAR1_CH25_TR_CMD
0x40901E7C FULL Software triggers
19.2.27 CH 26
Register Name
Address Permission Description
PASS0_SAR1_CH26_TR_CTL
0x40901E80 FULL Trigger control.
PASS0_SAR1_CH26_SAMPLE_CTL
0x40901E84 FULL Sample control.
PASS0_SAR1_CH26_POST_CTL
0x40901E88 FULL Post processing control
PASS0_SAR1_CH26_RANGE_CTL
0x40901E8C FULL Range thresholds
PASS0_SAR1_CH26_INTR
0x40901E90 FULL Interrupt request register.
PASS0_SAR1_CH26_INTR_SET
0x40901E94 FULL Interrupt set request register
PASS0_SAR1_CH26_INTR_MASK
0x40901E98 FULL Interrupt mask register.
PASS0_SAR1_CH26_INTR_MASKED
0x40901E9C FULL Interrupt masked request register
PASS0_SAR1_CH26_WORK
0x40901EA0 FULL Working data register
PASS0_SAR1_CH26_RESULT
0x40901EA4 FULL Result data register
PASS0_SAR1_CH26_GRP_STAT
0x40901EA8 FULL Group status register
PASS0_SAR1_CH26_ENABLE
0x40901EB8 FULL Enable register
PASS0_SAR1_CH26_TR_CMD
0x40901EBC FULL Software triggers
19.2.28 CH 27
Register Name Address Permission Description
PASS0_SAR1_CH27_TR_CTL
0x40901EC0 FULL Trigger control.
PASS0_SAR1_CH27_SAMPLE_CTL
0x40901EC4 FULL Sample control.
PASS0_SAR1_CH27_POST_CTL
0x40901EC8 FULL Post processing control
PASS0_SAR1_CH27_RANGE_CTL
0x40901ECC FULL Range thresholds
PASS0_SAR1_CH27_INTR
0x40901ED0 FULL Interrupt request register.
PASS0_SAR1_CH27_INTR_SET
0x40901ED4 FULL Interrupt set request register
PASS0_SAR1_CH27_INTR_MASK
0x40901ED8 FULL Interrupt mask register.
PASS0_SAR1_CH27_INTR_MASKED
0x40901EDC FULL Interrupt masked request register
PASS0_SAR1_CH27_WORK
0x40901EE0 FULL Working data register
PASS0_SAR1_CH27_RESULT
0x40901EE4 FULL Result data register
PASS0_SAR1_CH27_GRP_STAT
0x40901EE8 FULL Group status register
PASS0_SAR1_CH27_ENABLE
0x40901EF8 FULL Enable register
PASS0_SAR1_CH27_TR_CMD
0x40901EFC FULL Software triggers
19.2.29 CH 28
Register Name Address Permission Description
PASS0_SAR1_CH28_TR_CTL
0x40901F00 FULL Trigger control.
PASS0_SAR1_CH28_SAMPLE_CTL
0x40901F04 FULL Sample control.
1084
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers