Infineon TRAVEO T2G - 3.8.3.28 CM0 P_SCS_DEMCR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.28 CM0P_SCS_DEMCR
Description:
Debug Exception and Monitor Control Register
Address:
0xE000EDFC
Offset:
0xDFC
Retention:
Retained
IsDeepSleep:
No
Comment:
Manages vector catch behavior and enables the DWT.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] VC
_CORERE
SET [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] VC
_HARDER
R [10:10]
None [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:25] DWTENA
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 VC_CORERESET RW R 0 Enable Reset Vector Catch. This causes a Local reset
to halt a running system. If DHCSR.C_DEBUGEN is
set to 0, the processor ignores the value of this bit.
10 VC_HARDERR RW R 0 Enable halting debug trap on a HardFault exception. If
DHCSR.C_DEBUGEN is set to 0, the processor
ignores the value of this bit.
24 DWTENA RW R 0 Global enable for all features configured and controlled
by the DWT unit. When DWTENA is set to 0 DWT
registers return UNKNOWN values on reads. In
addition, it is IMPLEMENTATION DEFINED whether
the processor ignores writes to the DWT while
DWTENA is 0.
191
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers