Infineon TRAVEO T2G - 23.9.35 SCB_INTR_SPI_EC_MASK

Technical Reference Manual 002-29852 Rev. *B
23.9.35 SCB_INTR_SPI_EC_MASK
Description:
Externally clocked SPI interrupt mask
Address:
0x40600EC8
Offset:
0xEC8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] EZ_READ
_STOP
[3:3]
EZ_WRITE
_STOP
[2:2]
EZ_STOP
[1:1]
WAKE_UP
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 WAKE_UP RW R 0 Mask bit for corresponding bit in interrupt request
register.
1 EZ_STOP RW R 0 Mask bit for corresponding bit in interrupt request
register.
2 EZ_WRITE_STOP RW R 0 Mask bit for corresponding bit in interrupt request
register.
3 EZ_READ_STOP RW R 0 Mask bit for corresponding bit in interrupt request
register.
1433
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers