Infineon TRAVEO T2G - 5.1.35 CPUSS_RAM1_PWR_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.35 CPUSS_RAM1_PWR_CTL
Description:
RAM 1 power control
Address:
0x40201388
Offset:
0x1388
Retention:
Retained
IsDeepSleep:
No
Comment:
This register controls the system SRAM 1 power states. System SRAM 1 consists of a single
power partition.
Default:
0xFA050003
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] PWR_MODE [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name VECTKEYSTAT [23:16]
Bits 31 30 29 28 27 26 25 24
Name VECTKEYSTAT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 PWR_MODE RW R 3 Power mode.
OFF 0 See RAM0_PWR_MACRO_CTL.
RESERVED 1 undefined
RETAINED 2 See RAM0_PWR_MACRO_CTL.
ENABLED 3 See RAM0_PWR_MACRO_CTL.
16:31 VECTKEYSTAT R 64005 See RAM0_PWR_MACRO_CTL.
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2022-04-18
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