Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.14 TCPWM_GRP_CNT_TR_IN_SEL0
Description:
Counter input trigger selection register 0
Address:
0x40380044
Offset:
0x44
Retention:
Retained
IsDeepSleep:
No
Comment:
Used to select triggers for specific counter events.
Default:
0x100
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CAPTURE0_SEL [7:0]
Bits 15 14 13 12 11 10 9 8
Name COUNT_SEL [15:8]
Bits 23 22 21 20 19 18 17 16
Name RELOAD_SEL [23:16]
Bits 31 30 29 28 27 26 25 24
Name STOP_SEL [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 CAPTURE0_SEL RW R 0 Selects one of the up to 256 input triggers as a
capture0 trigger. Input trigger 0 is always '0' and input
trigger 1 is always '1'. If existing, the one-to-one trigger
inputs 'tr_one_cnt_in' (different to each counter) are
selected by setting 2 and above. The settings above
are used for the general purpose trigger inputs
'tr_all_cnt_in' connected to all counters selected.
In the PWM, PWM_DT and PWM_PR modes this
trigger is used to switch the values if the compare and
period registers with their buffer counterparts.
8:15 COUNT_SEL RW R 1 Selects one of the 256 input triggers as a count trigger.
In QUAD mode, this is the first phase (phi A). Default
setting selects input trigger 1, which is always '1'.
Note: In the modes: TIMER, CAPTURE, PWM,
PWM_DT, and SR, If the counter is externally
triggered ( COUNT_SEL > 1), an external trigger will
be required for each TR_CMD to execute. For
example, a write to TR_CMD.START will not start the
counter until the trigger selected by COUNT_SEL
asserts. The next trigger will increment the counter
since the counter is now running. This goes for all
TR_CMD fields.
16:23 RELOAD_SEL RW R 0 Selects one of the 256 input triggers as a reload
trigger.
In QUAD mode, this is the index or revolution pulse. In
these modes, it will update the counter with 0x8000
(counter midpoint) or 0x0000 depending on the
QUAD_RANGE_MODE.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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