Infineon TRAVEO T2G - 13.5.1.2 FAULT_STRUCT_STATUS

Technical Reference Manual 002-29852 Rev. *B
13.5.1.2 FAULT_STRUCT_STATUS
Description:
Fault status
Address:
0x4021000C
Offset:
0xC
Retention:
Retained
IsDeepSleep:
No
Comment:
This register uses cold reset (and is NOT affected by Active or DeepSleep reset). This allows
for failure analysis after a warm reset (DeepSleep reset).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] IDX [6:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALID
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:6 IDX RW W Undefined The fault source index for which fault information is
captured in DATA0 through DATA3. The fault
information is fault source specific and described
below.
Note: this register field (and associated fault source
data in DATA0 through DATA3) should only be
considered valid, when VALID is '1'.
MPU_0 0 Bus master 0 MPU/SMPU.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
MPU_1 1 Bus master 1 MPU. See MPU_0 description.
MPU_2 2 Bus master 2 MPU. See MPU_0 description.
MPU_3 3 Bus master 3 MPU. See MPU_0 description.
MPU_4 4 Bus master 4 MPU. See MPU_0 description.
MPU_5 5 Bus master 5 MPU. See MPU_0 description.
MPU_6 6 Bus master 6 MPU. See MPU_0 description.
MPU_7 7 Bus master 7 MPU. See MPU_0 description.
MPU_8 8 Bus master 8 MPU. See MPU_0 description.
MPU_9 9 Bus master 9 MPU. See MPU_0 description.
MPU_10 10 Bus master 10 MPU. See MPU_0 description.
MPU_11 11 Bus master 11 MPU. See MPU_0 description.
MPU_12 12 Bus master 12 MPU. See MPU_0 description.
918
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers