Infineon TRAVEO T2G - 7.5.3.10 CXPI_CH_TX_FIFO_CTL

Technical Reference Manual 002-29852 Rev. *B
7.5.3.10 CXPI_CH_TX_FIFO_CTL
Description:
TX FIFO control
Address:
0x40518080
Offset:
0x80
Retention:
Not Retained
IsDeepSleep:
No
Comment:
This is the transmit fifo control register
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] TRIGGER_LEVEL [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:18] FREEZE
[17:17]
CLEAR
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 TRIGGER_LEVEL RW R 0 Trigger level. When the TX FIFO has less entries than
the number of this field, a transmitter trigger event is
generated:
-INTR.TX_FIFO_TRIGGER = (#FIFO entries <
TRIGGER_LEVEL)
16 CLEAR RW R 0 This is a synchronous clear signal to the TX FIFO.
When '1', the TX FIFO content are cleared. If a quick
clear is required, the field should be set to '1' and
followed by '0'. If a clear is required for an extended
time, the field should be set to 1 during the complete
time.
17 FREEZE RW R 0 Freeze functionality:
'0': HW uses TX FIFO data and pops the data from the
TX FIFO for every HW read.
'1': HW read from TX FIFO does not pop the data from
the TX FIFO.
Note: Freeze functionality is for debug purpose only.
783
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers