Infineon TRAVEO T2G - 14.2.6 FLASHC_FM_SRAM_ECC_CTL1

Technical Reference Manual 002-29852 Rev. *B
14.2.6 FLASHC_FM_SRAM_ECC_CTL1
Description:
eCT Flash SRAM ECC control 1
Address:
0x402402B4
Offset:
0x2B4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] ECC_INJ_PARITY [6:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:6 ECC_INJ_PARITY RW R 0 7-bit parity for ECC error injection test of eCT Flash
SRAM ECC logic.
943
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers