Infineon TRAVEO T2G - 28.4.1.1.9 TCPWM_GRP_CNT_PERIOD_BUFF

Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.9 TCPWM_GRP_CNT_PERIOD_BUFF
Description:
Counter buffered period register
Address:
0x40380024
Offset:
0x24
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xFFFFFFFF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name PERIOD [7:0]
Bits 15 14 13 12 11 10 9 8
Name PERIOD [15:8]
Bits 23 22 21 20 19 18 17 16
Name PERIOD [23:16]
Bits 31 30 29 28 27 26 25 24
Name PERIOD [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 PERIOD RW RW 429496729
5
Additional buffer for counter PERIOD register.
In PWM_PR mode PEROD_BUFF defines the LFSR
polynomial. Each bit represents a tap of the shift
register which can be feed back to the MSB via an
XOR tree.
Examples for GRP_CNT_WIDTH = 16:
- Maximum length 16bit LFSR
- polynomial x^16 + x^14 + x^13 + x^11 + 1
- taps 0,2,3,5 -> PERIOD = 0x002d
- period is 2^16-1 = 65535 cycles
- Maximum length 8bit LFSR:
- polynomial x^8 + x^6 + x^5 + x^4 + 1
- taps 8,10,11,12 (realized in 8 MSBs of 16bit LFSR)
- period is 2^8-1 = 255 cycles
In SR mode PERIOD_BUFF defines which tap of the
shift register generates the PWM output signals. For a
delay of n cycles (from capture event to PWM output)
the bit CNT_WIDTH-n should be set to '1'. For a shift
register function only one tap should be use, i.e. a one-
hot value must be written to PERIOD_BUFF. If multiple
bits in PERIOD_BUFF are set then the taps are XOR
combined.
1804
2022-04-18
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