Infineon TRAVEO T2G - 3.8.7.4 CM0 P_MTB_BASE

Technical Reference Manual 002-29852 Rev. *B
3.8.7.4 CM0P_MTB_BASE
Description:
BASE register
Address:
0xF000300C
Offset:
0xC
Retention:
Retained
IsDeepSleep:
No
Comment:
Purpose: Indicates where the SRAM is located in the processor memory map. This register is
provided to enable auto discovery of the MTB SRAM location, by a debug agent.
Usage constraints: There are no additional usage constraints.
Configurations: Available in all MTB configurations.
Default:
0xF0010000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name BASE [7:0]
Bits 15 14 13 12 11 10 9 8
Name BASE [15:8]
Bits 23 22 21 20 19 18 17 16
Name BASE [23:16]
Bits 31 30 29 28 27 26 25 24
Name BASE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 BASE R R 402659737
6
The value provided is the value of the
SRAMBASEADDR[31:0] signal.
MTB SRAM base address in the processor memory
map, which is fixed for this platform.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers