Technical Reference Manual 002-29852 Rev. *B
2.3.2 CANFD_STATUS
Description:
Global CAN status register
Address:
0x40521004
Offset:
0x1004
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name STOP_ACK [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 STOP_ACK R RW 0 Clock Stop Acknowledge for each TTCAN IP.
These bits are directly driven by m_ttcan_clkstop_ack
of each TTCAN IP.
When this bit is set the corresponding TTCAN IP
clocks will be gated off, except HCLK will enabled for
each AHB write
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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