Infineon TRAVEO T2G - 28.4.1.1.13 TCPWM_GRP_CNT_TR_CMD

Technical Reference Manual 002-29852 Rev. *B
28.4.1.1.13 TCPWM_GRP_CNT_TR_CMD
Description:
Counter trigger command register
Address:
0x40380040
Offset:
0x40
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Enables software controlled operation for this counter.
Note: Synchronized operation on multiple counters can be done using trigger multipliers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] CAPTURE1
[5:5]
START
[4:4]
STOP [3:3] RELOAD
[2:2]
None [1:1] CAPTURE0
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CAPTURE0 RW1S RW1C 0 SW capture 0 trigger. When written with '1', a capture
0 trigger is generated and the HW sets the field to '0'
when the SW trigger has taken effect. It should be
noted that the HW operates on the counter frequency.
If the counter is disabled through CTRL.ENABLED, the
field is immediately set to '0'.
2 RELOAD RW1S RW1C 0 SW reload trigger. For HW behavior, see
COUNTER_CAPTURE0 field.
3 STOP RW1S RW1C 0 SW stop trigger. For HW behavior, see
COUNTER_CAPTURE0 field.
4 START RW1S RW1C 0 SW start trigger. For HW behavior, see
COUNTER_CAPTURE0 field.
5 CAPTURE1 RW1S RW1C 0 SW capture 1 trigger. For HW behavior, see
COUNTER_CAPTURE0 field.
1810
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers