Infineon TRAVEO T2G - 3.8.4 ROM; 3.8.4.1 CM0 P_ROM_ROM_SCS

Technical Reference Manual 002-29852 Rev. *B
3.8.4 ROM
3.8.4.1 CM0P_ROM_ROM_SCS
Description:
CM0+ CoreSight ROM Table Peripheral #0
Address:
0xE00FF000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xFFF0F003
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE R 429398016
3
Offset to SCS ROM Table
201
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers