Technical Reference Manual 002-29852 Rev. *B
7.5.3 CH
7.5.3.1 CXPI_CH_CTL0
Description:
Control 0
Address:
0x40518000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register contains controls for CXPI such as modes, offset, or master/slave.
This register is programmed before the start of a transaction and not to be change inflight of
any transaction. It can only be change during CXPI controller is quiescent.
Default:
0x10
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RXPIDZERO
_CHECK
_EN [7:7]
None [6:5] AUTO_EN
[4:4]
None [3:1] MODE [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] FILTER_EN
[8:8]
Bits 23 22 21 20 19 18 17 16
Name IFS [20:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
MASTER
[30:30]
None [29:28] BIT
_ERROR
_IGNORE
[27:27]
None [26:25] IBS [24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 MODE RW R 0 Mode of operation:
'0': NRZ mode.
'1': PWM mode.
NRZ 0 NRZ mode
PWM 1 PWM mode
4 AUTO_EN RW R 1 CXPI transceiver auto enable:
'0': Disabled.
'1': Enabled. The TX_RX_STATUS.EN_OUT field is
controlled by HW.
7 RXPIDZERO_CHECK
_EN
RW R 0 Receive PID Zero Check Enable.
0 - No action if received PID[6:0] = 0 and PID[7]=1'b1.
1 - If received PID[6:0] = 0 and PID[7]=1'b1, HW
(slave) does not clear CMD.RX_HEADER and will
anticipate receiving header again
(CMD.TX_HEADER=0). If CMD.TX_HEADER=1 in the
same scenario, then HW (slave) clears
CMD.RX_HEADER upon receiving the header follow
by transmit PID. This mode is useful for case where
polling method is used and CXPI controller is
configured as slave. This would reduce dependency
on SW to react to the header received within IBS=1.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
To Next Page
Loading...
