Infineon TRAVEO T2G - 23.9.21 SCB_TX_FIFO_STATUS

Technical Reference Manual 002-29852 Rev. *B
23.9.21 SCB_TX_FIFO_STATUS
Description:
Transmitter FIFO status
Address:
0x40600208
Offset:
0x208
Retention:
Not Retained
IsDeepSleep:
No
Comment:
This register is not used in EZ and CMD_RESP modes.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name USED [7:0]
Bits 15 14 13 12 11 10 9 8
Name SR_VALID
[15:15]
None [14:9] USED [8:8]
Bits 23 22 21 20 19 18 17 16
Name RD_PTR [23:16]
Bits 31 30 29 28 27 26 25 24
Name WR_PTR [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:8 USED R W 0 Amount of entries in the transmitter FIFO. The value of
this field ranges from 0 to FF_DATA_NR
(EZ_DATA_NR/2).
15 SR_VALID R W 0 Indicates whether the TX shift registers holds a valid
data frame ('1') or not ('0'). The shift register can be
considered the top of the TX FIFO (the data frame is
not included in the USED field of the TX FIFO). The
shift register is a working register and holds the data
frame that is currently transmitted (when the protocol
state machine is transmitting a data frame) or the data
frame that is transmitted next (when the protocol state
machine is not transmitting a data frame).
16:23 RD_PTR R W 0 FIFO read pointer: FIFO location from which a data
frame is read by the hardware.
24:31 WR_PTR R W 0 FIFO write pointer: FIFO location at which a new data
frame is written.
1419
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers