Infineon TRAVEO T2G - 3.8.3.10 CM0 P_SCS_CPUID

Technical Reference Manual 002-29852 Rev. *B
3.8.3.10 CM0P_SCS_CPUID
Description:
CPUID Register
Address:
0xE000ED00
Offset:
0xD00
Retention:
Retained
IsDeepSleep:
No
Comment:
Contains the part number, version, and implementation information that is specific to this
processor.
Default:
0x410CC601
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name REVISION [3:0]
Bits 15 14 13 12 11 10 9 8
Name PARTNO [15:8]
Bits 23 22 21 20 19 18 17 16
Name VARIANT [23:20] CONSTANT [19:16]
Bits 31 30 29 28 27 26 25 24
Name IMPLEMENTER [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 REVISION R 1 Indicates revision. In ARM implementations this is the
minor revision number n in the pn part of the rnpn
revision status, see Product revision status on Arm
TRM page xii. For release r0p1.
4:15 PARTNO R 3168 Indicates part number, Cortex-M0+
16:19 CONSTANT R 12 Indicates the architecture, ARMv6-M
20:23 VARIANT R 0 Implementation defined. In ARM implementations this
is the major revision number n in the rn part of the rnpn
revision status, Product revision status on Arm TRM
page xii.
24:31 IMPLEMENTER R 65 Implementer code for ARM.
171
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers