Infineon TRAVEO T2G - 3.8.3.6 CM0 P_SCS_ICER

Technical Reference Manual 002-29852 Rev. *B
3.8.3.6 CM0P_SCS_ICER
Description:
Interrupt Clear Enable Register
Address:
0xE000E180
Offset:
0x180
Retention:
Retained
IsDeepSleep:
No
Comment:
Disables, or reads the enabled state of one or more interrupts
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CLRENA [7:0]
Bits 15 14 13 12 11 10 9 8
Name CLRENA [15:8]
Bits 23 22 21 20 19 18 17 16
Name CLRENA [23:16]
Bits 31 30 29 28 27 26 25 24
Name CLRENA [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 CLRENA RW1C R 0 Disables, or reads the enabled state of one or more
interrupts. Each bit corresponds to the same
numbered interrupt.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers