Infineon TRAVEO T2G - 24.1.48 SFLASH_TOC2_FLAGS

Technical Reference Manual 002-29852 Rev. *B
24.1.48 SFLASH_TOC2_FLAGS
Description:
Controls default configuration
Address:
0x17007DF8
Offset:
0x7DF8
Retention:
Retained
IsDeepSleep:
No
Comment:
If TOC2 is erased (default), Flash boot assumes TOC2_FLAGS = 0x0000_0243
Default:
0x243
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SWJ_PINS_CTL [6:5] LISTEN_WINDOW [4:2] CLOCK_CONFIG [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] FB_BOOTLOADER_CTL
[10:9]
APP_AUTH
_CTL [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 CLOCK_CONFIG RW 3 Indicates clock frequency configuration. The clock
should stay the same after Flash Boot execution.
0 = 8 MHz, IMO, no FLL
1 = 25 MHz, IMO + FLL
2 = 50 MHz, IMO + FLL
3 = Use ROM boot clocks configuration (default)
2:4 LISTEN_WINDOW RW 0 Determines the Listen window to allow sufficient time
to acquire debug port. When CLOCK_CONFIG is set
to 3, these window times are calculated assuming
ROM boot clock is at 100MHz.
0 = 20 ms (Default)
1 = 10 ms
2 = 1 ms
3 = 0 ms (No Listen window)
4 = 100 ms
5:6 SWJ_PINS_CTL RW 2 Determines if SWJ pins are configured in SWJ mode
by Flash boot.
Note: SWJ pins may be enabled later in the user code.
0 = Do not enable SWJ pins in Flash boot. Listen
window is skipped.
1 = Do not enable SWJ pins in Flash boot. Listen
window is skipped.
2 = Enable SWJ pins in Flash boot (default).
3 = Do not enable SWJ pins in Flash boot. Listen
window is skipped.
7:8 APP_AUTH_CTL RW 0 Determines if the application image digital signature
verification (authentication) is performed:
0 = Authentication is enabled (default).
1 = Authentication is disabled.
2 = Authentication is enabled (recommended).
3 = Authentication is enabled.
1610
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers