Infineon TRAVEO T2G - 5.1.13 CPUSS_CM4_VECTOR_TABLE_BASE

Technical Reference Manual 002-29852 Rev. *B
5.1.13 CPUSS_CM4_VECTOR_TABLE_BASE
Description:
CM4 vector table base
Address:
0x40200200
Offset:
0x200
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [9:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR22 [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR22 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
10:31 ADDR22 RW 0 Address of CM4 vector table. This register is used for
CM4 warm and cold boot purposes: the CM0+ CPU
initializes the CM4_VECTOR_TABLE_BASE register
and the CM4 boot code uses the register to initialize
the CM4 internal VTOR register.
Note: the CM4 vector table is at an address that is a
1024 B multiple.
715
2022-04-18
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