Infineon TRAVEO T2G - 2.3.9.6.31 CANFD_CH_RXF1 S

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.31 CANFD_CH_RXF1S
Description:
Rx FIFO 1 Status
Address:
0x405200B4
Offset:
0xB4
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] F1FL [6:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] F1GI [13:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:22] F1PI [21:16]
Bits 31 30 29 28 27 26 25 24
Name DMS [31:30] None [29:26] RF1L
[25:25]
F1F [24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:6 F1FL R RW 0 Rx FIFO 1 Fill Level
Number of elements stored in Rx FIFO 1, range 0 to
64.
8:13 F1GI R RW 0 Rx FIFO 1 Get Index
Rx FIFO 1 read index pointer, range 0 to 63.
This field is updated by the software writing to
RxF1A.FAI
16:21 F1PI R RW 0 Rx FIFO 1 Put Index
Rx FIFO 1 write index pointer, range 0 to 63.
24 F1F R RW 0 Rx FIFO 1 Full
0= Rx FIFO 1 not full
1= Rx FIFO 1 full
25 RF1L R RW 0 Rx FIFO 1 Message Lost
This bit is a copy of interrupt flag IR.RF1L. When
IR.RF1L is reset, this bit is also reset.
0= No Rx FIFO 1 message lost
1= Rx FIFO 1 message lost, also set after write
attempt to Rx FIFO 1 of size zero
30:31 DMS R RW 0 Debug Message Status
00= Idle state, wait for reception of debug messages,
DMA request is cleared
01= Debug message A received
10= Debug messages A, B received
11= Debug messages A, B, C received, DMA request
is set
88
2022-04-18
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