Infineon TRAVEO T2G - 5.1.41 CPUSS_AP_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.41 CPUSS_AP_CTL
Description:
Access port control
Address:
0x40201414
Offset:
0x1414
Retention:
Retained
IsDeepSleep:
No
Comment:
This register enables individual test controller access ports (AP). Note that the system AP is
further controlled by a AP specific MPU, the SMPU and PPUs. The system AP MPU may be
programmed to provide no or limited test controller access capabilities.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] SYS
_ENABLE
[2:2]
CM4
_ENABLE
[1:1]
CM0
_ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] SYS
_DISABLE
[18:18]
CM4
_DISABLE
[17:17]
CM0
_DISABLE
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CM0_ENABLE RW R 0 Enables the CM0 AP interface:
'0': Disabled.
'1': Enabled.
1 CM4_ENABLE RW R 0 Enables the CM4 AP interface:
'0': Disabled.
'1': Enabled.
2 SYS_ENABLE RW R 0 Enables the system AP interface:
'0': Disabled.
'1': Enabled.
16 CM0_DISABLE RW1S R 0 Disables the CM0 AP interface:
'0': Enabled.
'1': Disabled.
Typically, this field is set by the Cypress boot code
with information from eFUSE. The access port is only
enabled when CM0_DISABLE is '0' and
CM0_ENABLE is '1'.
17 CM4_DISABLE RW1S R 0 Disables the CM4 AP interface:
'0': Enabled.
'1': Disabled.
Typically, this field is set by the Cypress boot code
with information from eFUSE. The access port is only
enabled when CM4_DISABLE is '0' and
CM4_ENABLE is '1'.
743
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers