Infineon TRAVEO T2G - 4.13.3 FPB; 4.13.3.1 CM4_FPB_CTRL

Technical Reference Manual 002-29852 Rev. *B
4.13.3 FPB
4.13.3.1 CM4_FPB_CTRL
Description:
FlashPatch Control Register
Address:
0xE0002000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
The FP_CTRL Register characteristics are:
Purpose: Provides FPB implementation information, and the global enable for the FPB unit.
Usage constraints: There are no usage constraints.
Configurations: Always implemented.
Attributes: See Table C1-23.
Default:
0x260
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name NUM_CODE_LO [7:4] None [3:2] KEY [1:1] ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None
[15:15]
NUM_CODE_HI [14:12] NUM_LIT [11:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name REV [31:28] None [27:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ENABLE RW R 0 Enable bit for the FPB:
0 Flash Patch Breakpoint disabled.
1 Flash Patch Breakpoint enabled.
A Power-on reset clears this bit to 0.
1 KEY RW R 0 On any write to FP_CTRL, this bit must be 1. A write to
the register with this bit set to zero is ignored. The
Flash Patch Breakpoint unit ignores the write unless
this bit is 1. This bit is RAZ.
4:7 NUM_CODE_LO RW R 6 The least significant bits, being bits[3:0], of
NUM_CODE, the number of instruction address
comparators.
If NUM_CODE[6:0] is zero, the implementation does
not support any instruction address comparators.
These bits are read only.
8:11 NUM_LIT RW R 2 The number of literal address comparators supported,
starting from NUM_CODE upwards. UNK/SBZP if
Flash Patch is not implemented. Flash Patch is not
implemented if
FP_REMAP[29] is 0.
If this field is zero, the implementation does not
support literal comparators. These bits are read-only.
12:14 NUM_CODE_HI RW R 0 The most significant bits, being bits[6:4], of
NUM_CODE, the number of instruction address
comparators, see bits[7:4].
These bits are read only.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers