Infineon TRAVEO T2G - 4.13.1.3 CM4_ITM_TPR

Technical Reference Manual 002-29852 Rev. *B
4.13.1.3 CM4_ITM_TPR
Description:
ITM Trace Privilege Register
Address:
0xE0000E40
Offset:
0xE40
Retention:
Retained
IsDeepSleep:
No
Comment:
Characteristics and bit assignments of the ITM_TPR register.
Purpose: Enables an operating system to control the stimulus ports that are accessible by
user code.
Usage constraints: You can only write to this register in privileged mode.
Configurations: This register is available if the ITM is configured in your implementation.
Attributes: Refer to the ITM register summary table.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] PRIVMASK [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 PRIVMASK RW R 0 Bit mask to enable tracing on ITM stimulus ports:
bit [0] = stimulus ports [7:0]
bit [1] = stimulus ports [15:8]
bit [2] = stimulus ports [23:16]
bit [3] = stimulus ports [31:24]
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2022-04-18
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