Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.52 CANFD_CH_TTOCN
Description:
TT Operation Control
Address:
0x40520114
Offset:
0x114
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TMC [7:6] RTIE [5:5] SWS [4:3] SWP [2:2] ECS [1:1] SGT [0:0]
Bits 15 14 13 12 11 10 9 8
Name LCKC
[15:15]
None
[14:14]
ESCN
[13:13]
NIG [12:12] TMG
[11:11]
FGP [10:10] GCS [9:9] TTIE [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 SGT RW R 0 Set Global time
Writing a '1' to SGT sets TTOST.WGDT if the node is
the actual Time Master. SGT is reset after one
Host clock period. The global time preset takes effect
when the node transmits the next reference
message with the Master_Ref_Mark modified by the
preset value written to TTGTP.
1 ECS RW R 0 External Clock Synchronization
Writing a '1' to ECS sets TTOST.WECS if the node is
the actual Time Master. ECS is reset after one
Host clock period. The external clock synchronization
takes effect at the start of the next basic cycle.
2 SWP RW R 0 Stop Watch Polarity
0= Rising edge trigger
1= Falling edge trigger
3:4 SWS RW R 0 Stop Watch Source
00= Stop Watch disabled
01= Actual value of cycle time is copied to
TTCPT.SWV
10= Actual value of local time is copied to
TTCPT.SWV
11= Actual value of global time is copied to
TTCPT.SWV
5 RTIE RW R 0 Register Time Mark Interrupt Pulse Enable
Register time mark interrupts are configured by
register TTTMK. A register time mark interrupt pulse
with the length of one NTU is generated when the time
referenced by TTOCN.TMC (cycle, local, or
global) equals TTTMK.TM, independent of the
synchronization state.
0= Register Time Mark Interrupt output m_ttcan_rtp
disabled
1= Register Time Mark Interrupt output m_ttcan_rtp
enabled
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
To Next Page
Loading...
