Infineon TRAVEO T2G - 3.8.3.23 CM0 P_SCS_MPU_RBAR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.23 CM0P_SCS_MPU_RBAR
Description:
MPU Region Base Address Register
Address:
0xE000ED9C
Offset:
0xD9C
Retention:
Retained
IsDeepSleep:
No
Comment:
Holds the base address of the region identified by MPU_RNR. On a write, can also be used to
update the base address of a specified region, in the range 0 to 15, updating MPU_RNR with
the new region number.
Normally, used with MPU_RBAR, see MPU Region Number Register, MPU_RNR.
If an implementation supports N regions then the regions number from 0 to (N-1). If N is less
than 16 the effect of writing a value of N or greater to the REGION field is UNPREDICTABLE.
Software can find the minimum size of region supported by an MPU region by writing all ones
to MPURBAR[31:5] for that region, and then reading the register to find the value saved to bits
[31:5]. The number of trailing zeros in this bit field indicates the minimum supported alignment
and therefore the supported region size. An implementation must support all region size
values from the minimum supported to 4GB, see the description of the MPU_RASR.SIZE field
in MPU Region Attribute and Size Register, MPU_RASR.
Software must ensure that the value written to the ADDR field aligns with the size of the
selected region.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] VALID [4:4] REGION [3:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:3 REGION RW R X On writes, can specify the number of the region to
update, see VALID field description.
On reads, returns bits [3:0] of MPU_RNR.
4 VALID RW R X On writes to the register, indicates whether the write
must update the base address of the
region identified by the REGION field. updating the
MPU_RNR to indicate this new region:
0 Update the base address of the region indicated by
MPU_RNR, ignoring the
value of the REGION field.
1 Update the least-significant four bits of the
MPU_RNR.REGION field with
MPU_RBAR.REGION field value, writing 0b0000 to
bits [7:4] of the
MPU_RBAR.REGION field, and updating the base
address of that region.
This bit reads as zero
8:31 ADDR RW R X Base address of the region.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers