Infineon TRAVEO T2G - 14.2.8 FLASHC_FM_SRAM_ECC_CTL3

Technical Reference Manual 002-29852 Rev. *B
14.2.8 FLASHC_FM_SRAM_ECC_CTL3
Description:
eCT Flash SRAM ECC control 3
Address:
0x402402BC
Offset:
0x2BC
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x1
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] ECC_INJ_E
N [4:4]
None [3:1] ECC
_ENABLE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] ECC_TEST
_FAIL [8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ECC_ENABLE RW R 1 ECC generation/check enable for eCT Flash SRAM
memory.
4 ECC_INJ_EN RW RW1C 0 eCT Flash SRAM ECC error injection test enable.
Follow the steps below for ECC logic test:
1. Write corrupted or uncorrupted 39-bit data to
FM_SRAM_ECC_CTL0/1 registers.
2. Set the ECC_INJ_EN bit to '1'.
3. Confirm that the bit ECC_TEST_FAIL is '0'. If this is
not the case, start over at item 1 because the eCT
Flash was not idle.
4. Check the corrected data in
FM_SRAM_ECC_CTL2.
5. Confirm that fault was reported to fault structure,
and check syndrome (only applicable if
corrupted data was written in step 1).
6. If not finished, start over at 1 with different data.
8 ECC_TEST_FAIL R W 0 Status of ECC test.
1 : ECC test failed because eCT Flash macro is busy
and using the SRAM.
0: ECC was performed.
945
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers