Infineon TRAVEO T2G - 5.1.18 CPUSS_CM0_INT0_STATUS

Technical Reference Manual 002-29852 Rev. *B
5.1.18 CPUSS_CM0_INT0_STATUS
Description:
CM0+ interrupt 0 status
Address:
0x40201100
Offset:
0x1100
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SYSTEM_INT_IDX [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] SYSTEM_INT_IDX [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name SYSTEM
_INT
_VALID
[31:31]
None [30:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:9 SYSTEM_INT_IDX R W Undefined Lowest CM0+ activated system interrupt index for CPU
interrupt 0.
Multiple system interrupts can be mapped on the same
CPU interrupt. The selected system interrupt is the
system interrupt with the lowest system interrupt index
that has an activated interrupt request at the time of
the fetch (system_interrupts[SYSTEM_INT_IDX] is '1').
The CPU interrupt handler SW can read
SYSTEM_INT_IDX to determine the system interrupt
that activated the handler.
31 SYSTEM_INT_VALID R W 0 Valid indication for SYSTEM_INT_IDX. When '0', no
system interrupt for CPU interrupt 0 is valid/activated.
720
2022-04-18
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