Infineon TRAVEO T2G - 26.8.23 CLK_TIMER_CTL

Technical Reference Manual 002-29852 Rev. *B
26.8.23 CLK_TIMER_CTL
Description:
Timer Clock Control Register
Address:
0x40261504
Offset:
0x1504
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Timer clock source selection register.
Default:
0x80070000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] TIMER
_SEL [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] TIMER_HF0_DIV [9:8]
Bits 23 22 21 20 19 18 17 16
Name TIMER_DIV [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLE
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TIMER_SEL RW R 0 Obsolete. Do not use in new designs. Keep default
value in new designs.
IMO 0 Obsolete. Do not use in new designs. Keep default
value in new designs.
HF0_DIV 1 Obsolete. Do not use in new designs.
8:9 TIMER_HF0_DIV RW R 0 Obsolete. Do not use in new designs. Keep default
value in new designs.
NO_DIV 0 Obsolete. Do not use in new designs. Keep default
value in new designs.
DIV_BY_2 1 Obsolete. Do not use in new designs.
DIV_BY_4 2 Obsolete. Do not use in new designs.
DIV_BY_8 3 Obsolete. Do not use in new designs.
16:23 TIMER_DIV RW R 7 Obsolete. Do not use in new designs. Keep default
value in new designs.
31 ENABLE RW R 1 Obsolete. Do not use in new designs. Keep default
value in new designs.
1662
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers