Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT6_TR_CMD
0x402881A8 FULL Channel software trigger
9.1.1.8 CH_STRUCT 7
Register Name Address Permission Description
DW0_CH_STRUCT7_CH_CTL
0x402881C0 FULL Channel control
DW0_CH_STRUCT7_CH_STATUS
0x402881C4 FULL Channel status
DW0_CH_STRUCT7_CH_IDX
0x402881C8 FULL Channel current indices
DW0_CH_STRUCT7_CH_CURR_PTR
0x402881CC FULL Channel current descriptor pointer
DW0_CH_STRUCT7_INTR
0x402881D0 FULL Interrupt
DW0_CH_STRUCT7_INTR_SET
0x402881D4 FULL Interrupt set
DW0_CH_STRUCT7_INTR_MASK
0x402881D8 FULL Interrupt mask
DW0_CH_STRUCT7_INTR_MASKED
0x402881DC FULL Interrupt masked
DW0_CH_STRUCT7_SRAM_DATA0
0x402881E0 FULL SRAM data 0
DW0_CH_STRUCT7_SRAM_DATA1
0x402881E4 FULL SRAM data 1
DW0_CH_STRUCT7_TR_CMD
0x402881E8 FULL Channel software trigger
9.1.1.9 CH_STRUCT 8
Register Name Address Permission Description
DW0_CH_STRUCT8_CH_CTL
0x40288200 FULL Channel control
DW0_CH_STRUCT8_CH_STATUS
0x40288204 FULL Channel status
DW0_CH_STRUCT8_CH_IDX
0x40288208 FULL Channel current indices
DW0_CH_STRUCT8_CH_CURR_PTR
0x4028820C FULL Channel current descriptor pointer
DW0_CH_STRUCT8_INTR
0x40288210 FULL Interrupt
DW0_CH_STRUCT8_INTR_SET
0x40288214 FULL Interrupt set
DW0_CH_STRUCT8_INTR_MASK
0x40288218 FULL Interrupt mask
DW0_CH_STRUCT8_INTR_MASKED
0x4028821C FULL Interrupt masked
DW0_CH_STRUCT8_SRAM_DATA0
0x40288220 FULL SRAM data 0
DW0_CH_STRUCT8_SRAM_DATA1
0x40288224 FULL SRAM data 1
DW0_CH_STRUCT8_TR_CMD
0x40288228 FULL Channel software trigger
9.1.1.10 CH_STRUCT 9
Register Name Address Permission Description
DW0_CH_STRUCT9_CH_CTL
0x40288240 FULL Channel control
DW0_CH_STRUCT9_CH_STATUS
0x40288244 FULL Channel status
DW0_CH_STRUCT9_CH_IDX
0x40288248 FULL Channel current indices
DW0_CH_STRUCT9_CH_CURR_PTR
0x4028824C FULL Channel current descriptor pointer
DW0_CH_STRUCT9_INTR
0x40288250 FULL Interrupt
DW0_CH_STRUCT9_INTR_SET
0x40288254 FULL Interrupt set
DW0_CH_STRUCT9_INTR_MASK
0x40288258 FULL Interrupt mask
DW0_CH_STRUCT9_INTR_MASKED
0x4028825C FULL Interrupt masked
DW0_CH_STRUCT9_SRAM_DATA0
0x40288260 FULL SRAM data 0
DW0_CH_STRUCT9_SRAM_DATA1
0x40288264 FULL SRAM data 1
DW0_CH_STRUCT9_TR_CMD
0x40288268 FULL Channel software trigger
9.1.1.11 CH_STRUCT 10
Register Name Address Permission Description
DW0_CH_STRUCT10_CH_CTL
0x40288280 FULL Channel control
DW0_CH_STRUCT10_CH_STATUS
0x40288284 FULL Channel status
DW0_CH_STRUCT10_CH_IDX
0x40288288 FULL Channel current indices
DW0_CH_STRUCT10_CH_CURR_PTR
0x4028828C FULL Channel current descriptor pointer
DW0_CH_STRUCT10_INTR
0x40288290 FULL Interrupt
DW0_CH_STRUCT10_INTR_SET
0x40288294 FULL Interrupt set
DW0_CH_STRUCT10_INTR_MASK
0x40288298 FULL Interrupt mask
DW0_CH_STRUCT10_INTR_MASKED
0x4028829C FULL Interrupt masked
DW0_CH_STRUCT10_SRAM_DATA0
0x402882A0 FULL SRAM data 0
DW0_CH_STRUCT10_SRAM_DATA1
0x402882A4 FULL SRAM data 1
DW0_CH_STRUCT10_TR_CMD
0x402882A8 FULL Channel software trigger
9.1.1.12 CH_STRUCT 11
Register Name Address Permission Description
DW0_CH_STRUCT11_CH_CTL
0x402882C0 FULL Channel control
DW0_CH_STRUCT11_CH_STATUS
0x402882C4 FULL Channel status
DW0_CH_STRUCT11_CH_IDX
0x402882C8 FULL Channel current indices
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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