Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR1_CH28_POST_CTL
0x40901F08 FULL Post processing control
PASS0_SAR1_CH28_RANGE_CTL
0x40901F0C FULL Range thresholds
PASS0_SAR1_CH28_INTR
0x40901F10 FULL Interrupt request register.
PASS0_SAR1_CH28_INTR_SET
0x40901F14 FULL Interrupt set request register
PASS0_SAR1_CH28_INTR_MASK
0x40901F18 FULL Interrupt mask register.
PASS0_SAR1_CH28_INTR_MASKED
0x40901F1C FULL Interrupt masked request register
PASS0_SAR1_CH28_WORK
0x40901F20 FULL Working data register
PASS0_SAR1_CH28_RESULT
0x40901F24 FULL Result data register
PASS0_SAR1_CH28_GRP_STAT
0x40901F28 FULL Group status register
PASS0_SAR1_CH28_ENABLE
0x40901F38 FULL Enable register
PASS0_SAR1_CH28_TR_CMD
0x40901F3C FULL Software triggers
19.2.30 CH 29
Register Name Address Permission Description
PASS0_SAR1_CH29_TR_CTL
0x40901F40 FULL Trigger control.
PASS0_SAR1_CH29_SAMPLE_CTL
0x40901F44 FULL Sample control.
PASS0_SAR1_CH29_POST_CTL
0x40901F48 FULL Post processing control
PASS0_SAR1_CH29_RANGE_CTL
0x40901F4C FULL Range thresholds
PASS0_SAR1_CH29_INTR
0x40901F50 FULL Interrupt request register.
PASS0_SAR1_CH29_INTR_SET
0x40901F54 FULL Interrupt set request register
PASS0_SAR1_CH29_INTR_MASK
0x40901F58 FULL Interrupt mask register.
PASS0_SAR1_CH29_INTR_MASKED
0x40901F5C FULL Interrupt masked request register
PASS0_SAR1_CH29_WORK
0x40901F60 FULL Working data register
PASS0_SAR1_CH29_RESULT
0x40901F64 FULL Result data register
PASS0_SAR1_CH29_GRP_STAT
0x40901F68 FULL Group status register
PASS0_SAR1_CH29_ENABLE
0x40901F78 FULL Enable register
PASS0_SAR1_CH29_TR_CMD
0x40901F7C FULL Software triggers
19.2.31 CH 30
Register Name Address Permission Description
PASS0_SAR1_CH30_TR_CTL
0x40901F80 FULL Trigger control.
PASS0_SAR1_CH30_SAMPLE_CTL
0x40901F84 FULL Sample control.
PASS0_SAR1_CH30_POST_CTL
0x40901F88 FULL Post processing control
PASS0_SAR1_CH30_RANGE_CTL
0x40901F8C FULL Range thresholds
PASS0_SAR1_CH30_INTR
0x40901F90 FULL Interrupt request register.
PASS0_SAR1_CH30_INTR_SET
0x40901F94 FULL Interrupt set request register
PASS0_SAR1_CH30_INTR_MASK
0x40901F98 FULL Interrupt mask register.
PASS0_SAR1_CH30_INTR_MASKED
0x40901F9C FULL Interrupt masked request register
PASS0_SAR1_CH30_WORK
0x40901FA0 FULL Working data register
PASS0_SAR1_CH30_RESULT
0x40901FA4 FULL Result data register
PASS0_SAR1_CH30_GRP_STAT
0x40901FA8 FULL Group status register
PASS0_SAR1_CH30_ENABLE
0x40901FB8 FULL Enable register
PASS0_SAR1_CH30_TR_CMD
0x40901FBC FULL Software triggers
19.2.32 CH 31
Register Name Address Permission Description
PASS0_SAR1_CH31_TR_CTL
0x40901FC0 FULL Trigger control.
PASS0_SAR1_CH31_SAMPLE_CTL
0x40901FC4 FULL Sample control.
PASS0_SAR1_CH31_POST_CTL
0x40901FC8 FULL Post processing control
PASS0_SAR1_CH31_RANGE_CTL
0x40901FCC FULL Range thresholds
PASS0_SAR1_CH31_INTR
0x40901FD0 FULL Interrupt request register.
PASS0_SAR1_CH31_INTR_SET
0x40901FD4 FULL Interrupt set request register
PASS0_SAR1_CH31_INTR_MASK
0x40901FD8 FULL Interrupt mask register.
PASS0_SAR1_CH31_INTR_MASKED
0x40901FDC FULL Interrupt masked request register
PASS0_SAR1_CH31_WORK
0x40901FE0 FULL Working data register
PASS0_SAR1_CH31_RESULT
0x40901FE4 FULL Result data register
PASS0_SAR1_CH31_GRP_STAT
0x40901FE8 FULL Group status register
PASS0_SAR1_CH31_ENABLE
0x40901FF8 FULL Enable register
PASS0_SAR1_CH31_TR_CMD
0x40901FFC FULL Software triggers
19.3 SAR 2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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