Technical Reference Manual 002-29852 Rev. *B
3.8.4.9 CM0P_ROM_ROM_PID2
Description:
CM0+ CoreSight ROM Table Peripheral ID #2
Address:
0xE00FFFE8
Offset:
0xFE8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0xB
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE R 11 Peripheral ID #2
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers