Infineon TRAVEO T2G - 26.8.50.11.4 MCWDT_CTR_WARN_LIMIT

Technical Reference Manual 002-29852 Rev. *B
26.8.50.11.4 MCWDT_CTR_WARN_LIMIT
Description:
MCWDT Subcounter Warn Limit Register
Address:
0x4026800C
Offset:
0xC
Retention:
Retained
IsDeepSleep:
No
Comment:
Warn limit for this MCWDT subcounter. Writes are ignored when locked (i.e. corresponding
MCWDT[i]_LOCK.WDT_LOCK<>0). This register may be written while the counter is running,
but new values may take up to 2 clk_lf cycles to take effect. Before changing the limit, it is
recommended to set the service bit for this subcounter within the configured limits. This
prevents possible unintended actions caused by the updated limits.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name WARN_LIMIT [7:0]
Bits 15 14 13 12 11 10 9 8
Name WARN_LIMIT [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 WARN_LIMIT RW R 0 Warn limit for this MCWDT subcounter. See
WARN_ACTION.
1718
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers