Technical Reference Manual 002-29852 Rev. *B
26.8.40 RES_CAUSE2
Description:
Reset Cause Observation Register 2
Address:
0x40261804
Offset:
0x1804
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Indicates the cause for the latest reset(s) that occurred in the system. Note that resets due to
power up and brown-outs below state retention voltages in regulated and unregulated
domains cannot be distinguished from each other. All bits in this register assert when the
corresponding reset cause occurs and must be cleared by firmware. These bits are cleared by
hardware only during XRES, POR or after a detected brown-out.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name RESET_CSV_HF [7:0]
Bits 15 14 13 12 11 10 9 8
Name RESET_CSV_HF [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:17] RESET
_CSV_REF
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 RESET_CSV_HF RW1C A 0 Clock supervision logic requested a reset due to loss
or frequency violation of a high-frequency clock. Each
bit index K corresponds to a HFCLK<K>.
Unimplemented clock bits return zero.
16 RESET_CSV_REF RW1C A 0 Clock supervision logic requested a reset due to loss
or frequency violation of the reference clock source
that is used to monitor the other HF clock sources.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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